In advanced sub-32 nanometer (nm) technologies, a replacement gate (RMG) is employed with a pre/post metal anneal (PMA). The high-k stack thermal budget, coupled with the PMA high temperature, may impact the thermal stability of the silicides. As such, a silicide last process may be required. However, the high-k metal gate must then be well-protected against the stripping of un-reacted wet nickel (Ni).
Another issue is the tight gate-to-gate spacing and the design rule (DR) requirement to place a contact there between. Adverting to FIG. 1A, the gate-to-gate pitch is getting so narrow that placing a contact 101 between two gates 103 using direct patterning is challenging. The contact size must be small. As shown, contact critical dimension (CD) 105 equals gate-to-gate space 107 minus 2 times the gate-to-contact distance 109. If the gate-to-contact distance 109 does not take into account the minimum gate-to-contact distance, to prevent gate-to-contact dielectric breakdown (illustrated at 111 in FIG. 1B) and gate-to-contact shorts (illustrated at 113 in FIG. 1C), plus an overlay margin, then any misalignment during contact lithography would cause dielectric breakdown due to a high electric field or a direct gate-to-contact short. Accordingly, contact size is restricted for direct patterning.
Due to the small contact size for the direct patterned method, not only is the contact resistance high, but also variation in resistance is large because of CD variation. A self-aligned contact (SAC) method for RMG processes (illustrated in FIG. 2A with contact 201 between two gates 203) achieves lower resistance and minimal variation, as shown in FIG. 2B.
A known silicide last process flow is illustrated in FIG. 3 and schematically illustrated in FIGS. 4A through 4C. Adverting to FIGS. 3 and 4A, a substrate 401 is provided (step 301), a transistor with a dummy gate is formed on the substrate (step 303), a first ILD 403 is deposited (step 305) and polished (step 307). The polysilicon gate is then removed (step 309) followed by removal of the gate oxide (step 311). A high-k metal gate is then formed by depositing a high-k dielectric 405 (step 313), annealing the dielectric (step 315), depositing a metal layer 407 (step 317), and performing chemical mechanical polishing (CMP) (step 319). In step 321, a second ILD layer 409 is deposited in which contact trenches 411 are etched (step 323) and a nickel (Ni) layer is deposited (step 325).
As illustrated in FIG. 4B, the Ni is annealed (step 327), forming silicide 415, and the unreacted metal is removed (step 329). The contact trenches are then filled with metal 417 (step 331), and the surface is polished by CMP (step 333), as shown in FIG. 4C. Since the contacts that are formed by this process are not self-aligned, damage to the high-k metal gate due to contact etch will occur if there is misalignment. Moreover, the small contact size may adversely affect the amount of Ni that is deposited on the source/drain. As such, silicides may not form adequately.
A conventional method of forming an SAC employs a gate oxidation scheme to form a protective layer on top of a tungsten (W) gate. If silicides are formed early in the process (i.e., silicide first), the gate stack and silicides are subjected to another possibly high thermal budget, which may affect stability. There is potential Vt impact on the gate during gate oxidation due to oxygen ingress into the high-k dielectric. If a gate oxide exists on the gate pad, then contact on the gate pad cannot be achieved simultaneous with source/drain contact. If no gate oxide exists, then contact etching will damage the gate pad. The recessed metal gate suggests that the dummy polysilicon gate height needs to be significantly larger than conventional to meet final metal gate resistance requirements. This implies more shadowing and limitation on halo tilt for SCE control. Due to the structure, weak points exist at high-k dielectric edges that could cause potential gate-to-contact shorts. Further, the weak points also reduce immunity to un-reacted Ni wet strip, if a silicide last process is employed. Overall, there is a high process risk.
A need therefore exists for methodology enabling a silicide last approach with formation of SAC, with improved overlay tolerance and increased contact size, and the resulting devices.